Writing Testbenches using SystemVerilog
Writing Testbenches using SystemVerilog by Janick Bergeron, published by Springer US on October 29, 2010, is a comprehensive resource that delves into the critical aspect of verification in hardware design. This softcover reprint of the hardcover first edition from 2006 spans 412 pages and is presented in English. The book addresses the significant amount of effort dedicated to verification within hardware design groups, emphasizing the importance of debugging and correctness checking activities beyond merely writing and running testbenches.
Readers will find a detailed exploration of various techniques and approaches to verification, highlighting the flexibility in coding styles and languages that can be utilized. The text discusses the challenges faced in achieving functional designs that meet intended specifications and timelines, particularly in the context of modern ASIC and FPGA technologies. By examining the implications of an informal verification process, the book underscores the necessity for a well-structured approach to ensure successful product development in the fields of electronics and circuit design.
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If you survey hardware design groups, you will learn that between 60% and 80% of their effort is dedicated to verification. This may seem unusually large, but I include in “verification” all debugging and correctness checking activities, not just writing and running testbenches. Every time a hardware designer pulls up a waveform viewer, he or she performs a verification task. With today’s ASIC and FPGA sizes and geometries, getting a design to fit and run at speed is no longer the main challenge. It is to get the right design, working as intended, at the right time. Unlike synthesizable coding, there is no particular coding style nor language required for verification. The freedom of using any l- guage that can be interfaced to a simulator and of using any features of that language has produced a wide array of techniques and approaches to verification. The continued absence of constraints and historical shortage of available expertise in verification, c- pled with an apparent under-appreciation of and under-investment in the verification function, has resulted in several different ad hoc approaches. The consequences of an informal, ill-equipped and understaffed verification process can range from a non-functional design requiring several re-spins, through a design with only a s- set of the intended functionality, to a delayed product shipment.
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