System-level Test and Validation of Hardware/Software Systems
System-level Test and Validation of Hardware/Software Systems by Zebo Peng, published by Springer Science & Business Media on April 7, 2005, is a comprehensive exploration of the challenges and advancements in system-on-chip (SOC) design. This edition spans 179 pages and is presented in English. The book addresses the shift in test and validation activities from traditional levels of abstraction to a system-level approach, highlighting the need for updated tools and methodologies to support this transition.
Readers will find a detailed overview of current validation and test techniques, encompassing various aspects such as modeling of bugs and defects, stimulus generation for validation, and design for testability. The content reflects the evolving landscape of hardware and software integration, emphasizing the importance of quality assurance and testing in the context of modern manufacturing technologies. This monograph serves as a valuable resource for those interested in the intersection of computer science, programming, and hardware development.
Official synopsis Publisher
New manufacturing technologies have made possible the integration of entire systems on a single chip. This new design paradigm, termed system-on-chip (SOC), together with its associated manufacturing problems, represents a real challenge for designers.
SOC is also reshaping approaches to test and validation activities. These are beginning to migrate from the traditional register-transfer or gate levels of abstraction to the system level. Until now, test and validation have not been supported by system-level design tools so designers have lacked the infrastructure to exploit all the benefits stemming from the adoption of the system level of abstraction. Research efforts are already addressing this issue.
This monograph provides a state-of-the-art overview of the current validation and test techniques by covering all aspects of the subject including:
- modeling of bugs and defects;
- stimulus generation for validation and test purposes (including timing errors;
- design for testability.
Publisher
Topics
FAQ
What is “System-level Test and Validation of Hardware/Software Systems” about?
Who is the author of “System-level Test and Validation of Hardware/Software Systems”?
When was “System-level Test and Validation of Hardware/Software Systems” published?
What is the ISBN for “System-level Test and Validation of Hardware/Software Systems”?
What are the book details (language, pages, edition)?
