System-level Test and Validation of Hardware/Software Systems
System-level Test and Validation of Hardware/Software Systems by Matteo Sonza Reorda, published by Springer London on November 10, 2010, is a softcover reprint of the hardcover first edition from 2005. This book explores the challenges posed by new manufacturing technologies that enable the integration of entire systems on a single chip, known as system-on-chip (SOC). It addresses the evolving landscape of test and validation activities, which are shifting from traditional levels of abstraction to a system-level approach, highlighting the need for appropriate design tools to support these advancements.
Readers will find a comprehensive overview of current validation and test techniques, covering critical aspects such as modeling of bugs and defects, stimulus generation for validation and test purposes, and design for testability. The book delves into the implications of SOC on the testing processes and the research efforts aimed at overcoming the limitations of existing methodologies. With 179 pages, this edition serves as a valuable resource for those interested in technology and engineering, particularly in the fields of electronics, circuits, and hardware programming.
Official synopsis Publisher
New manufacturing technologies have made possible the integration of entire systems on a single chip. This new design paradigm, termed system-on-chip (SOC), together with its associated manufacturing problems, represents a real challenge for designers.
SOC is also reshaping approaches to test and validation activities. These are beginning to migrate from the traditional register-transfer or gate levels of abstraction to the system level. Until now, test and validation have not been supported by system-level design tools so designers have lacked the infrastructure to exploit all the benefits stemming from the adoption of the system level of abstraction. Research efforts are already addressing this issue.
This monograph provides a state-of-the-art overview of the current validation and test techniques by covering all aspects of the subject including:
- modeling of bugs and defects;
- stimulus generation for validation and test purposes (including timing errors;
- design for testability.
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