Low Power Interconnect Design
Low Power Interconnect Design by Sandeep Saini, published by Springer New York on June 15, 2015, is a technical resource comprising 152 pages in English. This book provides practical solutions aimed at reducing delay and power consumption in on-chip interconnects and buses, addressing critical issues in modern electronics and systems architecture.
Readers will find an in-depth exploration of signal delay and power consumption challenges, along with potential solutions for delay and glitch removal. The text emphasizes the use of the Schmitt Trigger as an alternative to traditional buffer insertion methods for enhancing performance in VLSI interconnects. Additionally, the book discusses various bus coding techniques designed to minimize delay and power in address and data buses, making it a relevant resource for those interested in electronics and circuit design.
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This book provides practical solutions for delay and power reduction for on-chip interconnects and buses. It provides an in depth description of the problem of signal delay and extra power consumption, possible solutions for delay and glitch removal, while considering the power reduction of the total system. Coverage focuses on use of the Schmitt Trigger as an alternative approach to buffer insertion for delay and power reduction in VLSI interconnects. In the last section of the book, various bus coding techniques are discussed to minimize delay and power in address and data buses.
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