Defect and Fault Tolerance in VLSI Systems Volume 2

Cover of Defect and Fault Tolerance in VLSI Systems Volume 2 by C.H. Stapper
Author: C.H. Stapper
Publisher: Springer US
Year: 2013
Language: en
Edition: 1
Pages: 316
ISBN-13: 9781475799590
Dimensions:
Height: 10 inches
Length: 7.01 inches
Weight: 1.276 Pounds
Width: 0.75 inches
Editorial overview Touché

Defect and Fault Tolerance in VLSI Systems Volume 2 by C.H. Stapper, published by Springer US on May 5, 2013, is a comprehensive exploration of the critical need for defect-tolerance and fault-tolerance in the design of VLSI and WSI systems. This edition, consisting of 316 pages, addresses the challenges posed by higher circuit densities and complex application objectives, emphasizing the importance of these concepts for enhancing yield and reliability in integrated circuit design.

Readers will find a detailed examination of advanced methods for defect and fault control, which are essential for improving manufacturability and productivity in the field of electronics. The book discusses the evolution of this interdisciplinary research area, highlighting significant workshops and collaborative efforts that have shaped current practices. Topics such as technology and engineering, circuits, and electrical systems are woven throughout the text, providing a thorough understanding of the advancements in VLSI systems.


Official synopsis Publisher

Higher circuit densities, increasingly more complex application ohjectives, and advanced packaging technologies have suhstantially increased the need to incorporate defect-tolerance and fault-tolerance in the design of VLSI and WSI systems. The goals of defect-tolerance and fault-tolerance are yield enhancement and improved reliahility. The emphasis on this area has resulted in a new field of interdisciplinary scientific research. I n fact, advanced methods of defect/fault control and tolerance are resulting in enhanced manufacturahility and productivity of integrated circuit chips, VI.SI systems, and wafer scale integrated circuits. In 1987, Dr. W. Moore organized an “International Workshop on Designing for Yield” at Oxford University. Edited papers of that workshop were published in reference [II. The participants in that workshop agreed that meetings of this type should he con tinued. preferahly on a yearly hasis. It was Dr. I. Koren who organized the “IEEE Inter national Workshop on Defect and Fault Tolerance in VLSI Systems” in Springfield Massachusetts the next year. Selected papers from that workshop were puhlished as the first volume of this series [21.

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This page includes the available description and bibliographic details for “Defect and Fault Tolerance in VLSI Systems Volume 2” by C.H. Stapper. Synopsis preview: Higher circuit densities, increasingly more complex application ohjectives, and advanced packaging technologies have suhstantially increased the need to incorporate defect-tolerance and fault-tolerance in the design of V…
Who is the author of “Defect and Fault Tolerance in VLSI Systems Volume 2”?
“Defect and Fault Tolerance in VLSI Systems Volume 2” is credited to C.H. Stapper.
When was “Defect and Fault Tolerance in VLSI Systems Volume 2” published?
Publisher: Springer US. Year: 2013.
What is the ISBN for “Defect and Fault Tolerance in VLSI Systems Volume 2”?
ISBN-13: 9781475799590.
What are the book details (language, pages, edition)?
Language: en. Pages: 316. Edition: 1.

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