Logic Synthesis and Verification
Logic Synthesis and Verification by Soha Hassoun, published by Springer Science & Business Media in November 2001, is a comprehensive resource that explores the advancements in logic synthesis and verification over the past two decades. This 454-page edition presents a state-of-the-art view of the field, detailing the critical role these processes play in the development of modern electronic components. The book is written in English and features contributions from twenty-eight recognized leaders in the area, ensuring a thorough examination of key developments and future challenges.
Readers will find that the book consists of fifteen chapters, each dedicated to a distinct aspect of logic synthesis and verification. It provides essential information for seniors, graduate students, researchers, and developers of Computer-Aided Design (CAD) tools. The chapters are designed to facilitate in-depth study and understanding of the topics, filling a notable gap in existing CAD literature. With a focus on technology and engineering, this edition serves as a valuable reference for those engaged in the fields of computers, electronics, and information technology.
Official synopsis Publisher
Research and development of logic synthesis and verification have matured considerably over the past two decades. Many commercial products are available, and they have been critical in harnessing advances in fabrication technology to produce today’s plethora of electronic components. While this maturity is assuring, the advances in fabrication continue to seemingly present unwieldy challenges.
Logic Synthesis and Verification provides a state-of-the-art view of logic synthesis and verification. It consists of fifteen chapters, each focusing on a distinct aspect. Each chapter presents key developments, outlines future challenges, and lists essential references.
Two unique features of this book are technical strength and comprehensiveness. The book chapters are written by twenty-eight recognized leaders in the field and reviewed by equally qualified experts. The topics collectively span the field.
Logic Synthesis and Verification fills a current gap in the existing CAD literature. Each chapter contains essential information to study a topic at a great depth, and to understand further developments in the field. The book is intended for seniors, graduate students, researchers, and developers of related Computer-Aided Design (CAD) tools.
From the foreword: “The commercial success of logic synthesis and verification is due in large part to the ideas of many of the authors of this book. Their innovative work contributed to design automation tools that permanently changed the course of electronic design.” by Aart J. de Geus, Chairman and CEO, Synopsys, Inc.
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