Digital Hardware Testing Transistor-level Fault Modeling and Testing
Digital Hardware Testing Transistor-level Fault Modeling and Testing by Rochit Rajsuman, published by Artech House in 1992, is an illustrated edition comprising 317 pages. This book presents realistic transistor-level fault models and testing methods applicable to various types of circuits, focusing on design-for-testability and built-in self-test methods.
Readers will find a detailed discussion on boundary scan techniques and emerging technologies, including partial scan, cross check, and circular self-test-path. The content is aimed at those interested in technology and engineering, particularly in the fields of electrical and electronics circuits, integrated systems, and quality control in telecommunications. This edition serves as a comprehensive resource for understanding the intricacies of digital hardware testing.
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Digital Hardware Testing presents realistic transistor-level fault models and testing methods for all types of circuits. The discussion details design-for-testability and built-in self-test methods, with coverage of boundary scan and emerging technologies such as partial scan, cross check, and circular self-test-path.
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