The Verilog® Hardware Description Language
The Verilog® Hardware Description Language by Donald Thomas is a comprehensive guide published by Springer on October 8, 2008. This fifth edition, spanning 408 pages, is presented in English and serves as an essential resource for understanding the Verilog computer hardware description language. The book provides a structured approach to various topics, including tutorials on creating modules, testbenches, and behavioral modeling of combinational and sequential circuits.
Readers will find detailed explanations on procedural models, rules for synthesizing circuits, and insights into finite state machines. The content is designed to facilitate a clear understanding of both foundational and advanced concepts in Verilog. This edition is particularly useful for those looking to deepen their knowledge of hardware description languages and their applications in circuit design.
Official synopsis Publisher
XV From the Old to the New xvii Acknowledgments xx| Verilog A Tutorial Introduction Getting Started 2 A Structural Description 2 Simulating the binaryToESeg Driver 4 Creating Ports For the Module 7 Creating a Testbench For a Module 8 Behavioral Modeling of Combinational Circuits 11 Procedural Models 12 Rules for Synthesizing Combinational Circuits 13 Procedural Modeling of Clocked Sequential Circuits 14 Modeling Finite State Machines 15 Rules for Synthesizing Sequential Systems 18 Non-Blocking Assignment (“
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