VHDL for Logic Synthesis

Cover of VHDL for Logic Synthesis by Andrew Rushton
Year: 2011
Language: en
Edition: 3
Pages: 496
ISBN-13: 9780470688472
Dimensions:
Height: 9.700768 Inches
Length: 6.999986 Inches
Weight: 2.25091969502 Pounds
Width: 1.29921 Inches
Dewey Decimal: 621.395
Editorial overview Touché

VHDL for Logic Synthesis by Andrew Rushton, published by John Wiley & Sons on April 25, 2011, is a comprehensive guide designed to simplify the VHDL (Very High Speed Integrated Circuits Hardware Description Language) for engineers. This third edition has been extensively rewritten to incorporate the new VHDL-2008 features, making it a valuable resource for understanding the relationship between VHDL and hardware resulting from logic synthesis. Spanning 496 pages, the book covers topics from basic combinational logic to advanced themes such as developing custom packages and writing test benches.

Readers will find a structured approach that bridges the gap between theory and practical application, focusing on logic synthesis. The book includes a common VHDL subset applicable across various synthesis systems and emphasizes design styles that promote longevity and reusability. With a new chapter dedicated to large-scale design examples and extensive coverage of data path design, including arithmetic and logic circuits, this edition serves as a complete reference for professional hardware engineers and postgraduate students in microelectronics or digital design.


Official synopsis Publisher

Making VHDL a simple and easy-to-use hardware description language

Many engineers encountering VHDL (very high speed integrated circuits hardware description language) for the first time can feel overwhelmed by it. This book bridges the gap between the VHDL language and the hardware that results from logic synthesis with clear organisation, progressing from the basics of combinational logic, types, and operators; through special structures such as tristate buses, register banks and memories, to advanced themes such as developing your own packages, writing test benches and using the full range of synthesis types.

This third edition has been substantially rewritten to include the new VHDL-2008 features that enable synthesis of fixed-point and floating-point hardware. Extensively updated throughout to reflect modern logic synthesis usage, it also contains a complete case study to demonstrate the updated features.

Features to this edition include:

  • a common VHDL subset which will work across a range of different synthesis systems, targeting a very wide range of technologies
  • a design style that results in long design lifetimes, maximum design reuse and easy technology retargeting
  • a new chapter on a large scale design example based on a digital filter from design objective and design process, to testing strategy and test benches
  • a chapter on writing test benches, with everything needed to implement a test-based design strategy
  • extensive coverage of data path design, including integer, fixed-point and floating-point arithmetic, logic circuits, shifters, tristate buses, RAMs, ROMs, state machines, and decoders

Focused specifically on logic synthesis, this book is for professional hardware engineers using VHDL for logic synthesis, and digital systems designers new to VHDL but familiar with digital systems. It offers all the knowledge and tools needed to use VHDL for logic synthesis. Organised in themed chapters and with a comprehensive index, this complete reference will also benefit postgraduate students following courses on microelectronics or VLSI / semiconductors and digital design.

FAQ
What is “VHDL for Logic Synthesis” about?
This page includes the available description and bibliographic details for “VHDL for Logic Synthesis” by Andrew Rushton. Synopsis preview: Making VHDL a simple and easy-to-use hardware description language Many engineers encountering VHDL (very high speed integrated circuits hardware description language) for the first time can feel overwhelmed by it. This…
Who is the author of “VHDL for Logic Synthesis”?
“VHDL for Logic Synthesis” is credited to Andrew Rushton.
When was “VHDL for Logic Synthesis” published?
Publisher: John Wiley & Sons. Year: 2011.
What is the ISBN for “VHDL for Logic Synthesis”?
ISBN-13: 9780470688472.
What are the book details (language, pages, edition)?
Language: en. Pages: 496. Edition: 3.

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