Multi-Net Optimization of VLSI Interconnect
Multi-Net Optimization of VLSI Interconnect by Konstantin Moiseev, published by Springer New York on November 8, 2014, is a comprehensive resource that delves into layout design and migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. This edition spans 233 pages and is presented in English, offering insights into scaling-dependent models for interconnect power, delay, and crosstalk noise.
Readers will find a detailed exploration of various design optimization problems, including the minimization of interconnect power under delay constraints and strategies for achieving minimal delay in wire bundles within specified routing areas. This book serves as a reference for design methodologies and layout automation techniques, addressing the physical design challenges associated with interconnects in advanced integrated circuits.
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This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.
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